Gelsinger replied to a post by a prominent analyst, Patrick Moorhead, where it was initially claimed that Intel’s 18A wasn’t tested on a PDK 1.0 but rather an older design kit, which is why the yield rate figures are reported so low.
Well, he’s not technically wrong. You need the actual production metrics to say if he’s full of shit though.
It’s not the right measure for progress. It’s the right measure for viability. If yield is terrible, the end product may cost too much to market.
Tldr it should be yield rate per area
If yield rates aren’t a good metric, what does he think is then? It’s certainly not layoff numbers, or C-suite compensation.
If after all that investment you’re only able to produce TEN PERCENT of the product successfully, that’s a failure, by definition. Even if they quintuple the yields, that’s still incredibly poor
Gelsinger was hired as a known long time engineer, rather than as a business expert. I would trust his numbers from an engineering perspective, even though I was laid off under his rule
Only exception would be if they can produce those wafers at 1/10th of the previous cost, but I highly doubt that’s the case.
If it’s 1/10 of the cost of purchasing them from TSMC, it’s viable
All depends on the maturity of the process. 10% for a new design on a bleeding edge process is possibly viable. You’ll then tweak the design and process to get the yield up.
Yield over die area should be the metric.
If you have a chip that is 50% of the wafer area, a single fault will lead to a yield of 50%. Now compare it with a chip that is 1% of the wafer area, the same single fault gets a yield of 99%.
So comparing the yields of two processes without factoring in the die area is not a fair game.
